1. Field of the Invention
This invention relates to improvements in integrated circuit memory cell arrays, and more particularly to improvements in word line arrangements for memory cell arrays, to improvements in word line and subword line arrangements, and to improvements in subword line driver circuits and methods for using same.
2. Relevant Background
In the construction of semiconductor memory arrays, a number of individual memory cells are generally arranged in rows and columns. The term "row" is used to refer to the horizontally aligned memory cells served by a word line, and the term "column" is used to refer to the vertically aligned memory cells served by a bit line, although this nomenclature is arbitrary, and may be found in reversed form in the literature.
Typically, the word line is used to select or enable memory cells on the row in which the particular word line exists, and the bit line is used to select a cell at the intersection of the active word line row and the bit line column to carry an output signal representing the memory state of the cell that has been read, or to apply an input signal to be applied or written to the cell. The term "enabled" denotes the activation of a cell to a particular operational mode, such as reading, writing, or erasing. More particularly, during reading, writing, and erasing operations, each cell in the array may be either selected or deselected, with a particular desired operation performed on the selected cells, such as read, write, or erase.
As memory arrays become more and more dense, the array architecture is often broken down into blocks, with each block having its own set of memory cells and row and column lines. In some cell embodiments, for example, a number of blocks are contained in the memory array and are simultaneously read to provide a number of output bits on a plurality of output lines corresponding to a single multibit word contained in the memory.
A typical block oriented memory 10 of the prior art is shown in FIG. 1. The memory array 10 has two blocks, denoted "Block a" and "Block b". Generally, as shown, the blocks may be physically arranged horizontally with respect to each other in sets so that a word line extends horizontally across both (or a number of) blocks. It should be noted that sometimes second or more sets of horizontal blocks may be provided, commonly with the sets being vertically arranged with respect to each other.
Often in such block oriented memories, main word lines (MWLs) 11a-11d extend across both Block a and Block b to carry signals to enable or drive selected ones of several subword lines (SWL) 12a-12b to 15a-15b, where each SWL is on the same row but in different blocks in the array. For each MWL 11a-11d, a corresponding main word decoder/driver circuit (MWD) 25-28 is provided. Thus, as shown in FIG. 1, one MWD and an associated MWL are provided per row of cells (the MWL labels ending with small letters in the drawing to signify that each is unique and that they are sequential).
Generally, such block oriented memories have metal MWLs that can be selectively connected to one or more polysilicon SWLs, or to an intermediate SWL decoder/driver (SWD), such as the SWDs 17a-17b to 20a-20b shown. The connections and the SWD circuitry 17a-17b to 20a-20b may be oriented vertically, or orthogonally to the rows of the array.
Each SWL that is selected by its respective SWD has an associated number of memory cells, M, which it serves. Usually, the SWDs accept inputs from the MWLs and a block enabling signal, BLKa and BLKb (the lower case letter signifying which block the BLK is associated), on lines 30 and 31. The MWD and BLK signals allow each SWL to be separately enabled by the respective SWDs.
In some applications, the SWD circuitries 17a-20a to 17b-20b may be replaced with direct connections between the MWLs and all SWLs on the same row. In such cases, the BLK signals may not be necessary. The main reason that connections may be used instead of SWDs is to reduce the electrical resistance in the main row of cells by segmenting the main row of cells into sections of subrows of cells, allowing the MWL to be connected to the lower resistance SWLs. This implementation, however, does not allow the unique enabling of separate SWLs.
Depending on the technology in which such memory is built, the connections and the SWD circuitry can be larger than the row dimension, or pitch. However, this may become problematic, especially if the physical size of the memory cells on the row is very small. In addition, the MWDs 25-28 may be arranged side-by-side within the same tight row pitch. Thus, the MWDs, SWDs, the connections between the MWLs and the SWDs, and the SWDs and the SWLs may be done within the row pitch of the memory cells, and for very small memory cells, the scaling and circuit arrangement problems created can be significant.